1. Field of the Invention
The present invention relates to charge pump technology, and more particularly, to an output voltage adjustable charge pump for amplifying an input voltage to provide the desired output voltage.
2. Description of the Related Art
In a notebook computer, tablet computer, smart phone or any other electronic apparatus, an IC with charge pump is generally used for amplifying the input voltage to provide a high level of output voltage for the working of an internal working circuit.
FIG. 4 illustrates a charge pump according to the prior art. According to this design, the charge pump comprises a chip A1 and a package substrate A2 packaged on the chip A1. The chip A1 comprises a clock generator A11 and 1st through 9th transistors M1˜M9. The clock generator A11 is capable of generating a first clock pulse CK1 and a reversed second clock pulse CK2. When at the high voltage level, the first clock pulse CK1 and the second clock pulse CK2 have the voltage of VDD. When at the low voltage level, the first clock pulse CK1 and the second clock pulse CK2 have zero volt. Further, the 1st through 9th transistors M1˜M9 have a threshold voltage Vt. The charge pump is used in a circuit board A3 that comprises an input voltage Vin of voltage level VDD, 1st through 8th capacitors C1˜C8, and a voltage stabilizer capacitor Cext.
During charging period for the 1st capacitor C1, the first clock pulse CK1 and the second clock pulse CK2 are respectively at the low voltage level and the high voltage level, and therefore the even number transistors M2, M4, M6 and M8 are cut off, and the odd number transistors M1, M3, M5, M7 and M9 are conducted. At this time, the VDD input voltage Vin is transmitted through the 1st transistor M1 to produce a threshold Vt voltage drop, a voltage of VDD−Vt is produced at one end of the 1st capacitor C1, and the other end of the 1st capacitor C1 receives zero volt from the first clock pulse CK1, and thus the 1st capacitor C1 is charged to the voltage level of VDD−Vt.
During boosting period for the 1st capacitor C1, the first clock pulse CK1 and the second clock pulse CK2 are respectively at the high voltage level and the low voltage level, therefore the odd number transistors M1, M3, M5, M7 and M9 are cut off, and the even number transistors M2, M4, M6 and M8 are conducted. At this time, one end of the 1st capacitor C1 receives the voltage of VDD from the first clock pulse CK1. Because the 1st capacitor C1 has stored therein voltage of VDD−Vt, the other end of the 1st capacitor C1 has a voltage of 2VDD−Vt that is transmitted through the 2nd transistor M2 to produce a threshold Vt voltage drop, and a voltage of 2×(VDD−Vt) is produced at one end of the 2nd capacitor C2, and the other end of the 2nd capacitor C2 receives the voltage of zero volt from the second clock pulse CK2, and therefore the 2nd capacitor C2 is charged to 2×(VDD−Vt).
Subject to the aforesaid manner, the voltages of capacitors C3˜C8 can be regulated, enabling the emitter of the 9th transistor M9 to provide an output voltage Vout of 9×(VDD−Vt) that is then stabilized by the voltage stabilizer capacitor Cext and then outputted to the internal working circuit A4 of the electronic apparatus.
However, from the circuit diagram of the prior art design shown in FIG. 5, it can be seen that if the desired working voltage for the working circuit A4 is 5×(VDD−Vt), the chip A1 must have 1st through 5th transistors M1˜M5 built therein to match with 1st through 4th capacitors C1˜C4 of the circuit board A3 for generating 5×(VDD−Vt) output voltage, i.e., a different chip A1 of a different specification must be used with the circuit board A3 for generating a different working voltage, for example, 1st through 9th transistors M1˜M9 of the chip A1 are used to match with 1st through 8th capacitors C1˜C8 of the circuit board A3 for generating 9×(VDD−Vt) output voltage, or 1st through 5th transistors M1˜M5 of the chip A1 are used to match with 1st through 4th capacitors C1˜C4 of the circuit board A3 for generating 5×(VDD−Vt) output voltage. Therefore, one specification of prior art charge pump can simply provide one output voltage Vout for the working circuit A4 of the electronic apparatus. When intending to use the charge pump in a different electronic apparatus that requires a different working voltage, the internal circuit layout of the chip A1 and the wiring of the package substrate A2 must be relatively modified. Before vending of different specifications of chips A1, these chips A1 must be verified individually through an IC verification process before acceptance. The verification must be performed on the chip A1 as well as the package substrate A2. If the circuit design of the chip A1 or the wiring between the chip A1 and the package substrate A2 is changed, a new verification must be performed. Thus, preparing multiple chips A1 of different specifications for different applications to meet different requirements for providing different output voltages requires multiple verification procedures and long operating time, increasing the cost.
Therefore, it is desirable to provide a charge pump that eliminates the drawbacks of the aforesaid prior art design.